PCI
the first part of the seventh chapter in our series on How to
Write an Operating System
PCI
Overview
A friend once said that "hardware engineers live to make software
engineers lives hell." PCI is on of the exceptions that actually works in
a usefull manner. In most architecture the PCI bridge handles most
everything such as Memory Mapped IO, DMA, and I/O ports it you are on a
PC. All that you don't have to worry too much about except for
configuring it.
PCI, also, provides an intellegent configuration mechanism. Each
device has either 64 or 256 bytes of configuration space. The 64 bytes
are a standard header format. The last 192 bytes
are left for device specific configureation. By the time your OS boot the
BIOS/Firmware will have set most of the important information such as IRQ
and IO address. Your OS need only read these values and start using them.
Thats right no jumpers. No probing. Does it get any better than this?
Addresses in PCI
PCI has a special way of representing addresses when dealing with the
config space. Values not only include location but address type
(memory/io) and various other flags. The two formats are as follows:
Memory Address
| 31 |
4 |
3 |
2 |
1 |
0 |
| Base address |
P |
Type |
0 |
| P |
Prefetchable |
| Type |
| 00 |
Located anywhere in 32-bit address space |
| 01 |
Located below 1 MB |
| 10 |
Located anywhere in 64-bit address space |
| 11 |
Reserved |
|
IO Address
| 31 |
2 |
1 |
0 |
| Base address |
R |
1 |
Processor Implementations