Config Header Format

Vendor ID - 0x00

This is an assigned number unique to each PCI vendor. For a somewhat complete list of these have a look at Linux's pci.h.

Device ID - 0x02

This is a vendor assigned number specifing which device it is. For a somewhat complete list of these have a look at Linux's pci.h.

Command - 0x04

This is used to enable vaious types of PCI opperations

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Reserved						BBE	SSE	WC	PER	VPS	MWI	SC	BM	MA	IO

BBE:	Fast Back-to-back enable. Enables fast back-to-back transfers during busmastering. Only enable this if all devices on the bus cand do BBE
SSE:	System Error Enable. When set to one the devie can drive the SERR# line.
WC:	Wait Cycle Enable. Controls whether the device does address/data steping.
PER:	Parity Error Response. When set to one the device can report partiy errors.
VPS:	VGA Pallette Snoop Enable. Tells the device to enable VGA pallet snooping
MWI	Memory Write and Invalidate. Enables the device to generate memory write and invalidate comamnds. The cache line size must be set before this bit is set.
SC	Special Cycle Recognition. Enables the device to monitor for special cycles on the bus.
BM	Bus Maser Enable. Enables the device to become the bus master.
MA	Memory Access Enable. When enabled the device responds to memory requests.
IO	I/O Access Enable. When enabled the device responds to io requests.

Status - 0x06

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DPE	SSE	RMA	RTA	STA	DT		DPR	FBBC	UDF	66	Reserved

DPE	Detect Parity Error. Set by device when it has detected a parity error
SSE	Signalled System Error. Set by device when it has driven the SERR# line
RMA	Received Master-Abort. Set by master when its tranaction is terminated due to a master-abort.
RTA	Received Target-Abort. Set by master when its tranaction is terminated due to a target-abort.
STA	Signalled Target-Abort. Set by target when it terminates a tranaction by target-abort.
DT	DEVSEL Timing. Read only bits whcih define the slowest DEVSEL# timing for the device. 00b = fast 01b = medium 10b = slow 11b = reserved
DPR	Data Parity Reported. Set by the bus master when the reporting bus master was the initator and set the PERR# itself or detected it asserted by the target.
FBBC	Fast Back-to-Back Capable. Indicates whether the device can perform fast back-to-back transfers
UDF	UDF Supported. Set if the device supports user definable features
66	66MHz Capable. Set if device can run at 66MHz.

Revision - 0x08

8 bit value indicating the revision of the device.

Class Code Register - 0x09

Specifies which type of device it is. The class code register is devied up into 3 8 bit parts: Class Code, Sub-Class Code, and Prog. I/F.

23..16	Class Code
15..8	Sub-Class Code
7..0	Prog. I/F

Look at the Class Code Table for a list of what these mean.

Cache Line Size - 0x0c

This is the cache line size of the CPU. This is CPU dependant. It is important that devices which do DMA have this value.

Latency - 0x0d

Specifies the maximum number of PCI cycles the bus master can retain control fo the bus.

Header Type - 0x0e

The header type is devided into two sections. Bits 6..0 comprise the header type. Bit 7 is the single/multi funtion device flag (0=single 1=multi). The header type specifies the format of bytes 0x10 to 0x3f. The two defined types are 0x00, the standard header type (pictured above), and 0x01, PCI-PCI bridge.

Built In Self Test (BIST) - 0x0f

7	6	5	4	3	2	1	0
C	S	Reserved		Ret

C	BIST Capable
S	Start BIST
Ret	BIST Return Code

If the device is BIST Capable it must set the return code to 0 within 2 seconds of the Start BIST bit being set, otherwise an error has occured.

Base Address Registers 0-5 - 0x10-0x24

These are base addresses for memory maped/io maped communications with the device. The actual function of these registers are device specific

CardBus CIS Pointer - 0x28

If this device sits on both PCI and CardBus this is used to point to Card Information Structure (CIS).

Subsystem Vendor ID - 0x2c

Optional extra vendor info.

Subsystem ID - 0x2e

Optional extra subsystem info.

Expansion Rom Address - 0x30

Address that the expansion ROM of the device (i.e. network boot rom) is mapped in.

IRQ Line - 0x3c

The IRQ this device is routed through. In otherwords what IRQ will be triggered when this device generates an interrupt. This value does not actually affect the opperation of the device, rather it is a place for the BIOS/Firmware to inform the OS what has been configured.

Interupt Pin - 0x3d

Which of the 4 lines (INTA#, INTB#, INTC#, or INTD#) this device raises interrupts on. A value of 0 means not interrupt. A value between 1 and 4 corresponds to INTA# through INTD#. A single function device is required to use INTA#.

Min Grant - 0x3e

A read only register informing the reader of how long the device would like maintain control of the bus as a bus master. The value is in increments of 250ns.

Max Latency - 0x3f

"How often" the device needs to access the PCI bus. The value is in increments of 250ns.