80386 System Tables
a reference page in our series on How to Write an
Operating System
System Descriptor Types
Type | Meaning | Segment/Gate |
0 | Reserved |
1 | available 16-bit TSS | System segment |
2 | LDT | System segment |
3 | active 16-bit TSS | System segment |
4 | 16-bit Call Gate | Gate |
5 | Task Gate | Gate |
6 | 16-bit Interrupt Gate | Gate |
7 | 16-bit Trap Gate | Gate |
8 | Reserved |
9 | available 32-bit TSS | System segment |
10 | Reserved |
11 | active 32-bit TSS | System segment |
12 | 32-bit Call Gate | Gate |
13 | Reserved |
14 | 32-bit Interrupt Gate | Gate |
15 | 32-bit Trap Gate | Gate |
Task State Segment
Most of the fields in the TSS mirror the
32-bit register set.
MSW (upper 16 bits) | LSW (lower 16 bits) | Offset |
I/O Map Base
| T | +100 (64h) |
0 | LDTR | +96 (60h) |
0 | GS selector | +92 (5ch) |
0 | FS selector | +88 (58h) |
0 | DS selector | +84 (54h) |
0 | SS selector | +80 (50h) |
0 | CS selector | +76 (4ch) |
0 | ES selector | +72 (48h) |
EDI | +68 (44h) |
ESI | +64 (40h) |
EBP | +60 (3ch) |
ESP | +56 (38h) |
EBX | +52 (34h) |
EDX | +48 (30h) |
ECX | +44 (2ch) |
EAX | +40 (28h) |
eFlags
| +36 (24h) |
EIP | +32 (20h) |
CR3 (PDBR)
| +28 (1ch) |
0 | SS for CPL2 | +24 (18h) |
ESP for CPL2 | +20 (14h) |
0 | SS for CPL1 | +16 (10h) |
ESP for CPL1 | +12 (0ch) |
0 | SS for CPL0 | +8 (08h) |
ESP for CPL0 | +4 (04h) |
0 | Backlink | +0 (00h) |
- The I/O map base field is an offset from the beginning of
the TSS, pointing to the
I/O permissions map for this task.
- The T bit (the least significant bit of the word at offset 64h)
is the Trace Bit, and tells the processor to cause a Debug Exception
when this context is run.
- The backlink field holds a selector for the TSS that this
context was called from (only valid if running).